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MAX2769B
Universal GPS Receiver
CS
t CSH
SCLK
t CSS
t CSW
t DS
t DH
t CH
t CL
SDATA
DATA
MSB
DATA
LSB
ADDR
MSB
ADDR
LSB
Figure 5. 3-Wire Timing Diagram
Table 4. Serial-Interface Timing Requirements
SYMBOL
t CSS
t DS
t DH
t CH
t CL
t CSH
t CSW
PARAMETER
Falling edge of CS to rising edge of the first SCLK time.
Data to serial-clock setup time.
Data to clock hold time.
Serial clock pulse-width high.
Clock pulse-width low.
Last SCLK rising edge to rising edge of CS .
CS high pulse width.
TYP VALUE
10
10
10
25
25
10
1
UNITS
ns
ns
ns
ns
ns
ns
clock
Table 5. Default Register Settings Overview
REGISTER
NAME
CONF1
CONF2
CONF3
PLLCONF
DIV
FDIV
STRM
CLK
TEST1
TEST2
Maxim Integrated
ADDRESS
(A3:A0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
DATA
Configures RX and IF sections, bias settings for individual blocks.
Configures AGC and output sections.
Configures support and test functions for IF filter and AGC.
PLL, VCO, and CLK settings.
PLL main and reference division ratios, other controls.
PLL fractional division ratio, other controls.
DSP interface number of frames to stream.
Fractional clock-divider values.
Reserved for test mode.
Reserved for test mode.
18
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